1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically an erasable programmable read only semiconductor memory (called "EPROM" in this specification).
2. Description of Related Art
Conventional EPROMs have been composed of a number of erasable programmable read only memory cells (for example, floating gate type MOS-FETs (metal-oxide-semiconductor field effect transistor)) arranged in the form of a matrix having a plurality of row lines and a plurality of column lines. Sources of all the memory cells are connected in common to ground. The memory cells arranged in each one row has their gates connected in common to one corresponding row line, and the memory cells arranged in each one column has their sources connected in common to one corresponding row line. Each of the row lines is pulled through an associated resistor to a voltage called Vpp, and is connected to one corresponding output of a row decoder through a transfer gate which is formed of a depletion N-channel MOS-FET. Each of the column lines is connected through a corresponding column selection transistor of a column selector to a common node which is connected to a read circuit such as a sense amplifier, and which is also connected to the voltage Vpp through a write control gate adapted to be on-off controlled by a write signal. A gate of each column selection transistor of the column selector is pulled through an associated resistor to the voltage Vpp, and is connected to one corresponding output of a column decoder through a transfer gate which is formed of a depletion N-channel MOS-FET. Gates of the depletion N-channel MOS-FETs of the row decoder and the column decoder are connected in common to receive a control signal so that the depletion N-channel MOS-FETs are selectively turned on when data is read or written.
In the above mentioned EPROM, when data is read, the voltage Vpp is brought to a voltage equal to a drain voltage Vdd, and the control signal is brought to a high level which is also equal to the drain voltage Vdd. On the other hand, the write signal is brought to a low level which is equal to a ground level (GND). In this condition, assuming that a threshold of the depletion N-channel MOS-FETs is V.sub.TD, since the gates of the depletion N-channel MOS-FETs are applied with Vdd, a potential not greater than (Vdd+.vertline.V.sub.TD .vertline.) can pass through the transfer gates of the depletion N-channel MOS-FETs.
On the other hand, each of the row decoder and the column decoder outputs a high level (Vdd) from only one selected output and a low level (GND) from the other outputs, namely non-selected outputs. Therefore, the column selection transistor receiving the high level at its gate is turned on, so that one column line is selected by the turned-on column selection transistor. One memory cell is selected by the selected one column line and one row line supplied with the high level from the row decoder, so that the gate of the selected memory cell is supplied with Vdd, and the drain of the selected memory cell is applied with an operating point voltage of the sense amplifier. Here, assuming that Vdd=5 V, if a threshold V.sub.TM of the selected memory cell is 2 V, the selected memory cell is turned on, so that the sense amplifier outputs "0". On the other hand, if the threshold V.sub.TM of the selected memory cell is 6 V, the selected memory cell is turned off, so that the sense amplifier outputs "1". Thus, data stored in the selected memory cell is read through the selected one column line and the turned-on column selection transistor to the sense amplifier.
As mentioned above, all the outputs of the row decoder and the column decoder are connected to the voltage Vpp through the respective pull-up resistors. Since the pull-up resistors are set to have a high resistance (for example 1 M.OMEGA.), the non-selected outputs of the row decoder and the column decoder are maintained at a low level in the above mentioned data reading operation.
On the other hand, when data is written, the voltage Vpp is brought to a high voltage (for example, 12.5 V), and the control signal is brought to the low level (GND). Similarly to the case of the data reading, the column selector outputs the voltage Vdd from its selected output. Therefore, the depletion N-channel MOS-FET (of the transfer gate) is biased in such a manner that the drain voltage is Vpp (for example, 12.5 V), the source voltage is Vdd (for example, 5 V), and the gate is ground level. Here, since the condition for the cut-off of the depletion N-channel MOS-FET is Vdd&gt;.vertline.V.sub.TD .vertline., if Vdd=5 V and V.sub.TD =-2 V, the depletion N-channel MOS-FET is cut off. Therefore, the drain of the cut-off depletion N-channel MOS-FET is pulled up to the voltage Vpp by action of the pull-up resistor, so that the column selection transistor having the gate connected to the cut-off depletion N-channel MOS-FET is turned on. Namely, one column line is selected. On the other hand, the non-selected outputs of the column decoder are pulled up through the pull-up resistors. However, as mentioned above, since the pull-up resistors have the high resistance, the non-selected outputs of the column selector are maintained at the low level, and therefore, non-selected column selector transistors are maintained off. The row decoder similarly operates so that only one row line is selected and the other row lines are not selected.
In this condition, if the write signal is at a high level (Vpp), the gate of the selected memory cell is applied with the voltage Vpp, and the drain of the selected memory cell is applied with a voltage of (Vpp-V.sub.TN). As a result, the threshold V.sub.TM of the selected memory cell is shifted from 2 V to 6 V, and therefore, "1" is written. On the other hand, if the write signal is at a low level (GND), although the gate of the selected memory cell is applied with the voltage Vpp, since the drain of the selected memory cell is not applied with a high voltage, the threshold V.sub.TM of the selected memory cell is maintained at 2 V. Namely, a not-written condition is maintained.
Written memory cells can be erased by irradiation of ultraviolet rays. For example, the threshold of 6 V is returned to 2 V. Thus, it is possible to read data from arbitrary selected memory cell and to write data to arbitrary selected memory cell.
As mentioned above, the conventional EPROMs have used the depletion N-channel MOS-FETs in both of the column decoder and the row decoder. Therefore, a process for forming the depletion N-channel MOS-FETs has been required. This has been disadvantageous since the number of ion implantation steps is increased and since the total process for manufacturing the EPROM becomes long.
In a writing period, if Vdd is smaller than .vertline.V.sub.TD .vertline., the depletion N-channel MOS-FETs of the column decoder and the row decoder are not cut off, so that the selected outputs of the row decoder and the column decoder cannot be pulled up by the associated high resistance pull-up resistors. As a result, it becomes impossible to write.
In a reading period, on the other hand, in order to read data at a high speed, it is required that an ON resistance R.sub.D of the transfer gate (the depletion N-channel MOS-FET) is small, so that the row decoder and the column decoder can be driven at a high speed. Assuming that a drain voltage, a gate voltage and a source voltage of the transfer gate (the depletion N-channel MOS-FET) are Vdd, Vdd and (Vdd-.DELTA.v), respectively, this ON resistance R.sub.D is expressed in the following equation: ##EQU1##
Therefore, EQU R.sub.D =.DELTA.v/I.sub.D =-1/(.beta..sub.D .multidot.V.sub.TD)
Where .beta..sub.D is a coefficient
Accordingly, in order to read the data at a high speed, the value of .vertline.V.sub.TD .vertline. must be set at a large value, and on the other hand, in order to enable to write data at a low level of Vdd, the value of .vertline.V.sub.TD .vertline. must be set at a small value. Namely, it is very difficult to set the value of .vertline.V.sub.TD .vertline..